Refractive Labs

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01 · Why photonics

Copper can’t keep up.

A single strand of optical fiber carries more data than a bundle of copper the width of your arm, over longer distances, with a fraction of the energy per bit. For thirty years that was the story of the internet's backbone. It is now the story of what happens inside a data center, inside a rack, and soon inside a package.

Compute has grown roughly threefold every two years. The bandwidth connecting that compute has grown by less than half that. Every generation, more of the machine's time and power is spent waiting on wires. Electrical interconnect is running into hard limits of loss, heat, and reach. Photonics is the way through.

  • Peak hardware FLOPS 3.0× / 2 yrs
  • DRAM bandwidth 1.6× / 2 yrs
  • Interconnect bandwidth 1.4× / 2 yrs
Scaling of peak hardware FLOPS, DRAM bandwidth and interconnect bandwidth, 1996 to 2023 Log-scale chart. Peak FLOPS grow about 3 times every two years; DRAM bandwidth about 1.6 times; interconnect bandwidth about 1.4 times. Values normalised to the R10000 of 1997. 1× 100× 10,000× 1,000,000× 1996 2000 2004 2008 2012 2016 2020 2024 R10000 Itanium 2 GTX 580 K40 KNL TPUv3 A100 H100 GDDR3 GDDR4 GDDR5 HBM HBM2 HBM2E PCIe 1.0a PCIe 2.0 PCIe 3.0 NVLink 1.0 PCIe 5.0 NVLink 4.0
Adapted from Gholami, Yao, Kim, Hooper, Mahoney and Keutzer, “AI and Memory Wall”, arXiv:2403.14123 (2024), CC BY 4.0.

02 · Why now

The technology is getting ready. The demand is already here.

Silicon photonics has grown from a research curiosity into a manufacturable technology. Foundries run photonic processes on 300 mm wafers. Hyperscalers deploy optical links by the million. Co-packaged optics, optical switching, and photonic compute are moving from slides to silicon.

At the same time, the need has become acute. Frontier AI models are trained across hundreds of thousands of accelerators, and the links between them now set the ceiling on scale, cost, energy, and latency. Inside a scale-up domain, where every accelerator has to behave like part of one machine, latency may be the limit that matters most. The market is asking for photonic chips faster than the industry can design them.

03 · Why design must change

We design photonic chips the way we did twenty years ago.

A small number of specialists run slow electromagnetic simulations, tune geometries by hand, and iterate through tape-outs that each take months. A single component can consume weeks of expert time. A full chip takes more than a year. Most of that time goes to design and verification, not invention.

There are only a few thousand people in the world who can do this work, and demand for them outstrips supply many times over. Training more of them will not close the gap on any useful timescale. The tooling has to change.

Design must become faster, more automated, and grounded in measured silicon rather than approximate models, so that a small team can do what today takes a large one, and the industry can build the optical infrastructure the next decade of computing depends on.

Refractive Labs

Est. 2026